Hello folks in these next set of videos
I’ll be describing to you about the process technology of the
different steps which are involved in making the chips that you see on your ipad or your
iphone or your laptop computer And we will be going into pretty gory details
of how these chips are made. What are the different steps involved. But before I get into the nitty-gritty of
that, I want to give you a feel of how these actual chips look when
you open them up. So if you open up say a micro processor or your memory chip what does it actually
look like? If you take a picture from the top, or if
you take a cross section view. So, I want to just briefly describe to you in this video that
about three of these chips. The first being the microprocessor. Or this A5X microprocessor that you see in
your iPad. And then the second chip I want to
describe to you is this DRAM chip. And the third chip I want to describe is
this NAND flash memory. And these are the typical three components
that you see in any mobile devices. You always find a microprocessor. You always find a DRAM chip. This DRAM chip sometimes is stand alone. Sometimes it’s actually stacked on top of
your microprocessor. To save a space on your board and you
always find almost always find a NAND flash memory to store your
apps and store your data as well. So let’s start with this micro processor,
so if you open up this micro processor and look at its die this
is what it looks like. So these are shown here are three
generations of these microprocessor chips starting from
A4 to A5 to A5X. And then interesting observation about these dies
is that more than 50% of the area here, or more than half of the area on this die is covered by these Is occupied by, by these SRAM
cells. So if you take ten pictures of on this
die from the top there’s a large chance that five of them
would look something like this. So shown here is a six transistor SRAM cell.
So shown here is one of these unit cells which is six transistor SRAM cells.
And shown here is, is the, is the circuit diagram for the cell.
So this SRAM cells is is essentially consist of six transistors two of them it consists two of
these inverters. One of them drawn in green and the other one drawn in blue and they are cross
connected. And then you have these two pass-gate
transistors which connect which are used to essentially read the state of the cell.
So if, if you look at this picture over here.
You know one, one does this looks nothing like the second diagram
so where are these transistors located. So let me help you out a little bit, so let me help you out in locating these
transistors. So these these parallel lines over here
these are essentially the gate lines. And these perpendicular lines over here,
these are the active lines. So shown here are the, these two set of
lines, one of them are the gate and the other one are
active area. And so now let’s, let’s try and look at
these transistors. So we see that this inverter has an
inverter here, so the gate of these two transistors must
be connected. And they must be connected to the source
drain of these other two transistors. So two of these transistors which are
shown in green over here, they can be located over
here. So there’s a gate line running over here. So this is one of these transistors and this is the other of these green
transistors. And then the gate of this is connected to the source and drain
of these second inverter. And also the source drain of these two are connected, so these two would be
connected. this would be on another layer which is
not shown over here. And let’s look at this other inverters, so
this other inverter in blue could be drawn over here.
So there would be this gate and this gate line is not in common so this
would be the other transistor. And then they are connected to the source
and drain all this first first inverter. And then the source and drain of the
second inverter would be connected too. And the gate of this first inverter would
then connect to the source drain of the second inverter. So, as shown here are two inverters. And then they are connected using these pass-gate transistors, which are located
over here. So, this is the pass, first pass-gate transistor, and this is the second
pass-gate transistor. So, now, now we have been able to locate these are, these are, these are two
pass-gate transistors. And then there are these, two inverters
so, this is how the, the circuit diagram translates onto this
top view. And, this is the most compact way you can
you can pack these six transistors into your
onto your die. Now that we have enjoyed the aerial view,
let’s look at side view so lets if we take a cross section of
this die. So if we take a cross section of this die
and look at it side ways this is how it looks like, so this is a Image courtesy from chip
works. And, it shows how, how this looks like
from the side. So you can again see these individual transistors which would be somewhere over
here. And then you have these vias which are
connecting this transistor to these interconnect
lines. So you see multiple of these interconnect
lines. metal 1, metal 2, metal 7. And these are essentially routing all the
signals between these SRAM and then your logic circuitry.
And so on and so forth. And this is, this is showing a
cross-section view of A5 microprocessor from your iPad.
If you take a cross-section of your chip that is on your
laptop. So this is showing a cross-section view of
of Ivy Bridge processor, similar to Ivy Bridge processor from Intel.
So this is how it would look like, again you have your transistor located
somewhere over here. And then you have again these multiple
multiple levels of interconnects. So this would metal one, metal two, all
the way up to I think they have nine levels of
these interconnects. And these interconnects are slightly
different between your, between your A5
microprocessor and the chip from Intel.
So the chip A5 microprocessor you see that there are these two sets of pitches between your interconnects.
All your metal 1 to metal 4 have 1 pitch. And then the layers above them have.uh,
another pitch. And in the Intel microprocessor, you see
that all of the levels of metals have different pitch. So if the pitch here is x, the pitch here
is maybe 1.4x. And then the pitch of each of these
interconnects is continuously increasing as can be shown
on here. because they want to optimize, really
optimize the performance uh.u or minimize the delay that you get from
your interconnect. So this is really optimized for
performance to the very core. Where our, over here you are just living
with maybe two or three levels of pitches for your metal
interconnect. So again you you if you really zoom in
over here, you can locate these transistors are shown here is
a 32nm transistor from Intel. And over here you can see the source and
the drain. And this is the gate and there’s a Hi-K
layer, Hi-K Hi-K layer over here.
And then these are the contact, these are the contact plugs, which are connecting
your source and drain and connecting them to the inter, the
interconnects above. We took a look at the microprocessor chip.
So now let’s examine the DRAM DRAM chip.
So if you open up a DRAM die, this is how it looks like.
So most of the area on your DRAM chip is occupied by these banks of
memory. So each of them has many of these DRAM
cells. Each DRAM cell is essentially a one transistor, one capacitor cell. And you have eight of these DRAM banks
shown over here. In the middle also you have this
controller, circuitry. So what this controller circuitry does is it takes the command from your
microprocessor. And it decodes into this column address
and this row address. To go and read that, read or write that
particular set. And so majority of the area over here is
occupied by this banks of cells. And so if you, if you, if you took a cross
section. There’s a very large percentage that you
will end up on a something which looks like
this. And, the first thing that, you know, you,
if you look at this cross section is, is gee, you know, what
the heck is this, you know? So it, it looks something like either
antenna hanging in the sky or it looks like this looks like a
horn of a deer, right? So they. It looks like either antenna or horn of a
deer so What is this you know we were supposed to have
this nice one transistor one capacitor. So where are where is the transistor first
of all. So if you look very carefully the
transistor is located somewhere over here. So, you’ll have your transistor located
some were over here. So, this is your access transistor. And this antenna or these set of horns hanging in the sky these are
actually the capacitor. So, the way a DRAM cell works let me give you a very quick intro.
So the way a DRAM cell works is that you store a charge on this capacitor.
And then you have this access transistor whose purpose is to essentially
help access the charge on this capacitor. So the capacitor is charged and you turn
this transistor on. That charge will get transferred on this,
bit line. And then you sense that voltage increase
in the bit line due to this charge. And that’s how you read the state of this
set. So, a few requirements on on this
capacitor that you wanted to have as high of a capacitance, as
possible. So it can store a large quantity of
charge. On this transistor, one of the main
requirement is, it should have low off current so that the discharge
which is stored in your . In your capacitor does not leak away
through this transistor. So this antenna is this capacitor, and it, it’s a MIM capacitor, so you have a
metal, and you have an insulator, and you have
another metal. So if, if you take a more closer look at this, it on this capacitor, it looks
like this. So you have two of these metal layers. So you have one of these metal layers
which is Ti-nitride. So you have one layer of trinitride here,
you have another of this metal layer, so this is two metal layers.
Metal and then other metal layer, both of them
being Ti-nitride And in between you have this insulator
layer. So in between you have this Aluminum
oxide, which is an insulator, and that essentially
makes up this transistor. Make up this capacitor.
So again, if you take a top view it would look something like this.
So you have the multiple of these antennas or horns hanging up in the sky.
So you want to make the capacitor as capacitance of this capacitor as large
as possible. So one way to do that is essentially to increase the height of the antenna. So you can keep it increasing making
taller and taller But again one of the challenges there is that these
structure should not collapse. If they collapse they will short each
other so you definitely don’t want that to happen.
And the way its design like an antenna again to maximise this capacitance so
shown in this cartoon are a. Is this one transistor one capacitor
design. So you have a transistor over here which
is an access transistor and then you have
this capacitor. And this this is called a stacked capacitor
design because your capacity is stacked on top of
your transistors. And again one way to increase the, the
capacitance is to increase the surface area of this
capacitor. So one way to increase the surface area is
to essentially hollow this capacitor out. And now you get both surface area on the
outside and you get surface area on the inside.
So that’s why a design like an antenna. So you get both the surface area on the
outside and then you get the surface area on the
inside. And sometimes you’re actually roughen the
surface as well. So you make the surface rough because
essentially again that increases your surface area which increases the
capacitance of this capacitor.