Pin Diagram of 8086 Microprocessor – Microprocessor

Pin Diagram of 8086 Microprocessor – Microprocessor


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The 8 0 8 6 Microprocessor it was the first 16-bit Microprocessor and it is available you know 40 pin IC means this IC 8086 IC it has 40 pins and also this 8086 Microprocessor it is available in different clock rates so we can write your though feature of the a zero eight six microprocessor that it is a first 16-bit microprocessor it is a 40 pin chip and it is available in different clock rates like it’s clock rate can be five megahertz eight megahertz fine 10 megahertz so depending upon the clock rates value and there are various versions of this eight zero eight six microprocessor now coming to the mode of operation of the eight six eight zero eight six microprocessor it operates in two mode phone first is the maximum mode and second is the minimum mode okay so in minimum mode the microprocessor it works as a single processor and in maximum mode it works as a multiprocessor system okay so this is zero eight six microprocessor it can operate in single processor configuration also and in multiprocessor configuration also to achieve high performance now as this is H zero eight six microprocessor it has 40 pins so these 40 pins some of the pins they can operate in either maximum mode or minimum mode or both maximum and minimum moves okay so here we can write that some of the pins may have functions which are operated in the maximum mode or in the minimum mode or both the modes so the same pin it can be used in both the modes in minimum mode also and in maximum mode also minimum mode is the mode in which the eight zero eight six it operates in single-processor configuration and maximum mode is the mode in which the eight zero eight six it operates in multiprocessor configuration so let us now study the pin diagram of a zero eight six microprocessor which consists of 40 pins so let us first see the pin diagram so this is the pin diagram of eight zero eight six microprocessor you can see that it has 40 pins on one side it has 1 2 20 and on the other side it has 21 to 40 pins and every pin is assigned a signal here so let us see on pin number one we have the VSS or the ground from pin number two to pin number 16 we have the address and the data bus ad not to ad 14 then we have ad 15 here and a 16 17 18 and 19 so the address bus it is of twenty i’m the 0 8 6 microprocessor so we have the 20 address line starting from ad not to a 19 okay then we have nmi okay int our clock and again VSS ground we have 2 connections for the ground then 21 it is researched 22 ready test Q s 1 Q s naught then s naught s 1 s 2 log RQ g t1 r qg g naught then rd bar minimum and maximum mode bus high enable and s 7 these are the status signal 3s 4s 5s 6 and a 7 then we have the VCC where the +5 full power supply is connected now here you can see that two modes are described one is the maximum hood and other is the minimum mode so in the maximum mode these pins work and in minimum mode these pins 31 to 24 these pins they will have these signals okay which are described here written here like pin number 31 in minimum mode it will act as the hold signal 30 pin it will act as a child ei hold of knowledge then write this is memory and input/output operation this is data transmit and receive then this is data enable this is address latch enable and this is int a so these signals they will walk when de 8 0 8 6 it is operating in the minimum mode in maximum mode these fins will work as our q GT not the signals which are written here so you can see that there are some pins which have the functions in both the maximum mode and the minimum mode and some pins are there which have a particular function either in the maximum mode and the minimum mode so now let us study the description of all the pins of the 8 0 8 6 micro processor in detail first we will start with the power supply signals in the power supply signals we have the ground and the +5 pool power supply as the zero eight six it operates at the +5 full power supply so at the bit number forty +5 fools VCC is connected and ground is available at two pins pin number one and pin number 20 so for power supply signals eight zero eight six it uses so a zero eight six it uses +5 volts DC supply at pin number forty we have the VCC that is +5 volt connection and at pin number one and pin 20 they are acting as the ground okay then we have the frequency signals or the clock input so clock signal or clock input it is provided by pin number 19 you can see in the pin diagram that at pin number 19 we have the clock input now this clock input it provides the timing signals to the processor so that it can perform various operations so here I have written that this protocol signal it provides timing to the processor for operations now it 0 8 6 it has different versions like eight zero eight six eight zero eight six one eight zero eight six two and these versions they operate at different clock frequencies like five megahertz eight megawatts and ten megahertz so we can say that the operating frequency range of eight zero eight six it is between five megahertz to ten megahertz okay next we have the address and the data goes the 80286 microprocessor it has 16-bit data bus and 20-bit address bus so we can say here that it has 20 lines for address which are from a not to a 19 and it has 16 lines for data which are from the not to be 15 now these address and the data bus lines they are multiplexed with each other so 16 data lines and 16 address lines they will be multiplexed so when they are multiplex they are collectively known as the 16 address and data lines are multiplexed so they will be together known as ad not to AD 15 so in this pin diagram you can see that we have ad not to F if – 14 available from pin number 16 to pin number 2 and pin number 39 is also ad 15 so we have ad not to ad 14 which are from pin number 2 to pin number 16 and 80 15 it is available at pin number 39 now how to differentiate that on these 16 address and data lines when addresses available and when data is available so during the clock cycles of the microprocessor during the first clock cycle the addresses of on these address lines and after four clock cycle data will be available so if we divide these 16 address and data lines into 288 bit under lines then ad not 287 it will carry the lower order data byte and ad 8 to 80 15 it will carry higher order data byte okay now during first clock cycle address is available on these lines and after first clock cycle data is available on these lines so this 16-bit data it will be available at the 1802 87 and 88 to ad 15 and the 20-bit address it will be obtained by combining the 16-bit data ends ad not to AD 15 and then a 16 is 17 18 and a 19 okay so in this way we can get the complete 20-bit address and the 16-bit data next we have the address and the status signals you can see in the pin diagram that the address and the data bus they were multiplexed from 1802 ad 15 and the remaining address lines they can work as these fins 38 to 35 they can work as the four address lines also and as the for status signals also that is from s3 s4 s5 and s6 so here we will discuss the address and the status signals so this is like a 16 to a ninety or it can either focus is three two is six okay so these lines or these pens they can act both as the address bus also and as the status bus also so how it will be differentiated that at one time addresses available and at what time these pins are acting as the status signals so during the first clock cycle the address will be available and after the first clock cycle the status signals will be available okay so during the first clock cycle we can get the complete 20-bit address by the address lines ad notes to ad fifteen and a sixteen to a nineteen and after the first clock cycle the data in the address bus they will denote though they will represent the data and the a 16-2 a ninety-nine these pencil didn’t carry the status signals okay next we have s seven or bus hi enables this signal it is available at pin number thirty-four you can see that we have two signals means it can act as bus high enable also and it can act as the stable signal is seven also okay so let’s see that what is the function of this signal this bhe it stands for bus high enabled and it is available at pin number 34 so this singer bus hi enable it is used to indicate the transfer of data using the data bus D 18 to D 15 so the higher-order data byte that will be transferred by using this signal bus high enable now this signal it is low during the first clock signal so you can see here that it is an active low signal so it will be active during the first clock cycle and when it is active it means that the data available on the bus it is the higher-order data and that has to be transferred okay so this indicates the transfer of data using the data bus and the signal is low during the first clock cycle next we have the read signal this reads signal it is available at pin number 32 we have our D bar and its full-form is read so it is available at pin number 32 and this signal it is used to indicate the read operations means whenever the microprocessor it is performing the read operation then this signal is low because it is having a bar over it so it is an active low signal and this signal is used to perform the read operations okay so it means that whenever this signal is active it means that the microprocessor it is performing the read operation then we have ready this ready signal it is available at pin number 22 you can see at the pin number 22 we have this ready signal now this signal is used by the micro processors or by the peripheral devices peripheral devices means the input/output devices which are connected with the eight zero eight six microprocessor now it happens that whenever the peripheral devices they want to connect it with the processor so the eight zero eight six it is having a very high processing speed but there are some peripherals which do not have such high speed so if they want to cope up with the speed of the eight zero eight six micro processor then they send this ready signal the micro processor wait for some time till the input/output devices or the peripheral devices they come to with it or they match up with its speed so at that time the micro processor will wait for some time and then the input/output devices they are ready for communication with the micro processor then they send this ready signal so this ready signal it is used by the peripheral devices to indicate the the processor that it is ready for the transfer of data or we can say that it is ready for communication with it okay so this ready signal it is available at pin number 22 so this ready signal it is an active high signal and we can also say that it is an acknowledgement signal from the input/output devices that data it is ready for to be transferred means the device is ready for communication with the microprocessor and when this signal is high it indicates that device is ready for transferring the data and when this signal is low it indicates wait state which state means that when the signal is low it means that the input/output devices they are netted they are not ready for communication so the microprocessor it has to wait for some time so that the input/output devices they match up with its speed or they first finishes their current operation and then they will perform the transfer of data with the microprocessor so when this signal is low it indicates wait state for the microprocessor so this is the ready signal so next we have the int our signal this int our signal it is available at pin number 18 you can see in the pin diagram at pin number 18 we have ID of the full form of this signal it is interrupt request it means that when this signal is given to the microprocessor 8:08 6 it means that some peripheral or some input/output device they want to interrupt the microprocessor means they are sending or request to interrupt the microprocessor so that microprocessor first finishes its operation and then it executes the service routine of that interrupt okay so we have the signal int R this is interrupt request signal this signal is available at pin number 18 so this is an interrupt request signal idea now every time the microprocessor suppose it is executing an instruction so this instruction they will be executed in the form of flop cycles so at the end of the last clock cycle of each instructions means when the instruction is executed and the microprocessor reaches to the last clock cycle of that instruction then add that last clock cycle this instruction I this pin int R will be checked if this signal is active means this is given to the microprocessor then it means that microprocessor is interrupted and then microprocessor has to finish the execution of that instruction and then jump to the location or at which the service routine of the interrupt is written okay so this signal it is checked during the last stroke cycle of each instruction and when this signal is given it means that the microprocessor is interrupted at that point okay next we have nm i which is the non-maskable interrupt ni mine is available at pin number 17 and the full form of this is not non-maskable interrupt this signal means that the interrupt is given to the microprocessor and the microprocessor cannot mask or it cannot deny this interrupt it has to and every situation it has to execute that interrupts okay so next we have nmi non-maskable interrupt it is available at pin number 17 so this is a type of Indra which cannot be masked by the microprocessor and it is an edge triggered input which interrupts the microprocessor okay and it is available at pin number 17 next we have the test signal this state signal it is available at pin number 23 here we have at pin number twenty-three dot test signal this is an active flow signals so this signal is available at pin number 23 and this signal is like the wait state so when this signal it is because it’s an active low signal so when the signal is low then the microprocessor would continue its execution of the instructions means it will perform and it is going to operate in its normal functions okay normal mode now when the signal is high then the processor it has to wait for the idle State okay so when the signal is low the execution continues in its normal way but when the signal is high then the processor has to wait for the idle state so we can say that this signal it is used to make the microprocessor it is cognate ating with the peripheral devices where it has to wait for some time okay so this signal is just like a wait state for the microprocessor then we have MN 4mx but this signal it is available at pin number 33 you can see here we have MN and M X bar so when the signal the signal decides that whether the eight zero eight six it is operating in the maximum mode or in the minimum mode so when the signal it is low it means that it is operating in the maximum mode and then this signal is high then the eight zero eight six it is operating in the minimum mode minimum mode means that the processor it is in the single-processor configuration and maximum mode that means the processor it is operating in the multiprocessor configuration means there are several processors which are connected with each other so it is available at pin number 33 this is for minimum and maximum mode so this is the minimum maximum mode signal which indicates that in which mode of the processor is this operating ok so when this is high it means minimum mode is there and when it is low it means maximum mode is there then we have int a which is the interrupts of knowledge signal whenever the microprocessor it is interrupted by the peripheral or some input/output devices so in response to the interrupt request given by the peripheral devices to the processor the processor generates an output signal which is known as the interrupt acknowledgment signal this signal means that the microprocessor has received to the request of the peripheral devices that they want to interrupt the microprocessor and now the microprocessor has received that request ok so it is kind of an acknowledgement signal so this signal it is available at pin number 24 and the microprocessor saying this signal whenever it acknowledges an intra next we have the ele signal the full form of the signal is address latch enabled so by the name of this signal you can get an idea that this signal it is used to enable the latch on the address bus okay so the address will be available for a longer period of time and also it is used to demultiplex the address of the data buses this early signal it is available at pin number 25 so this signal it is available at pin number 25 and when a positive pulse means when the signal is high then each time the processor every time the processor begins any operation so every time the microprocessor it is a starting any operation likely right so any time when any operation is started this signal is high ok and when the signal is high it indicates that a valid address is available on the address and the data burst because we have the address and the data bus as multiplexed with each other that is ad not 280 15 so to distinguish that on these bus whether data is available or addresses are available this signal is used so when this signal is high it means that address is available on these buses ok so every time the microprocessor it is starting any operation like read operation write operation it needs the address of the memory location so before starting any operation a positive pulse means in this signal is active hi this signal will be generated ok next we have D in lattice data enable you can see that this D en it is available at pin number 26 okay so this pin these signals they are active in the minimum mode okay these al he int a which we have studied they are also applicable only in the minimum mode of operation so this is the data enable which is at pin number 26 now this data enable signal it is used to enable the trance receiver I see a 286 so this transfer see where it is a device which can transmit the data means it can transfer the data also or it can receive the data also so whenever we want to enable the day or whenever we want to transfer or receive the data from the 8 0 8 6 micro processor then this data enable signal is used because this signal it is going to enable the 8 2 8 6 trans receiver which is acting between the 8 0 8 6 processor and the input/output devices also the 1802 ad 15 address on the data bus it is carrying both the address and the data so if you want to separate the data from this bus then also this trans receiver is used so whenever we want the data to be available then we use this signal to enable the trans receiver I see a 286 next we have DT or the full form of this is data transmit or receive so this signal it is used to indicate the direction of flow of data means whether the data it is coming towards the 8 0 8 6 or it is going out of 8 0 8 6 so it is to indicate that the data transfer it is either the flow of data it is either towards or it is either outward from the 8 0 8 6 so this is for data transmit or receive this is available at pin number 27 so this signal it is used to decide the direction of flow through the trans receiver whether the data is transmitted or whether it is received so when this signal is high it means data is transmitted and when this signal is low it means the data is received because on the received we have a bar so it means that this will be active when its values low and this will be active when its value is high okay the next signal we have is M I so this signal it is for the memory and the input/output operations means this signal will indicate that the operation performed by the eight zero eight six it is either a memory operation or an input/output operation like whether it is memory read memory write or input/output reiden input/output right so this signal it is for memory at the input/output operations it is available at pin number 28 so this signal it is used to distinguish between the memory and the input/output operations when this signal is high it means that it is an input/output operation and when it is low it means that it’s a memory operation and it is available at pin number 28 next we have the signal WR this is for the right signal just like we have the read signal we have the right signal also which indicates that the operation performed by the microprocessor it’s a write operation like memory write or input/output right so this WR it is available at pin number 29 so this right signal it is used to write the data into the memory or the output device depending upon that bit operation is selected okay and this signal is an active low signal so when it is zero it value is zero then only the right operation will be performed next we have h lda and hold h lda it stands for the hold acknowledgement signal this acknowledgment signal it is used when the microprocessor it is performing the communication with the DMA controller and this is an acknowledgement signal for the hold signal given by the other processors so we can say that it is hold of knowledge mint or this signal indicates that it to the eight zero eight six eight has received the hold signal okay so it is just a response towards that it is available at pin number 30 and this signal of indicates the acknowledges the hold signal now next we have the whole signal now this hold signal indicates that there are some of the processors which are want to complicate with the microprocessor and they want that the microprocessor relieve the control of its buses to those processors so that the processors they can have control over the buses of eight zero eight six so hold it is our request which is given to the eight zero eight six that the other processors they want the control of it buses like address bus data bus and the control bus it is available at pin number 31 so we can say that these two signals are for the whole signals like DME execution DMA it is the direct memory SS controller we will study these two signals in detail when we study the interfacing of DMA without eight zero eight six microprocessor next we have the cue s 1 and Q s naught signal which are the cue status signals now we know that this 8 0 8 6 microprocessor it has a special feature of instruction q means that whenever it executes any instruction when it has the quality of prefetching six instructions at a time means that the operation code of six instructions can be fetched at the same time ok so these six instructions they will form a queue so what is the status of the queue that is revealed by the two signals Q s 1 and Q s not these two signals they have different combinations and those combination they will indicate different status of the queue these are available at pin number 24 and 25 so we have the conditions for these two signals Q s naught and Q s 1 first we can have 0 0 then 0 1 1 0 and 1 1 so when these two signals are 0 0 then no operation is there no operation will be performed when it is 0 1 then first bite so in the Q we have the opcodes for the instructions they will be stored so when this Q s naught and Q s 1 they are 0 1 then the first bite of the hood will be fetched from the cube then if if we have 1 0 then this is going to empty the Q and if it is 1 1 means subsequent bite from the cube subsequent bite means first bite is already being fetched so the bite which is next to this byte that will be fetched from the Q so depending upon the thickness of these two signals the following operations will be performed next we have s naught s 1 and s 2 these three are the status signals and these status signals they decide the type of operation performed by the 8:08 6 like whether it is memory read memory write input output read input output right or it’s the opcode fetch cycle so these operations they are decided by the three signals s naught s 1 and as to these are the status signals so these signals they provide the status of the operation and they are available at pin number 26 27 and 28 you can see in the block diagram we have 26 27 28 the 3 status signals is not s 1 mm is 2 so let us see the combination of these three signals that were the three combinations they describe the kind of operation we have H 2 s 1 and s naught we can have different combinations like 0 0 0 0 0 1 0 1 0 0 1 1 then we have 1 0 0 1 0 1 1 1 0 and 1 1 1 so 3 signals they can have the 8 combinations so when it is 0 0 0 it means interrupt acknowledgment means the processor it is going to acknowledge the interrupt and it is going to generate the int a signal okay then we have 0 0 1 so that will be an input-output read means no operation performed by the microprocessor will be an input-output read it is going to read the data from an input/output device then 0 1 0 it is input-output write 0 1 1 it will be the hold state 1 0 0 it is opcode fetch 1 0 1 memory read one one zero memory right and one one one it is passive so these eight combinations they decide that which is the status or which is the type of operation performed by the microprocessor next we have the signals lock you can see that in the block diagram we have ad finem in this Venn diagram we have the pin number 29 as the clock signal so this lock signal it indicates that the microprocessor it has locked its buses means like the other input output and the peripheral devices they cannot have a control over its buses okay so this signal it indicates that the other processor they should not ask the microprocessor for the control of its buses it is available at pin number 29 so this log signal it indicates other processors not to ask the CPU to leave the system bus this signal is activated this signal can be activated by writing the prefix log at in front of every instruction so we can write the lock prefix on any instruction so the next signals we have are the RQ g t 1 and r 2 g t not these are the requests and the grant signals so we can have the request and grant first then we have request and the ground zero signals so we can write here we have the request and grant signals so whenever the microprocessor means whenever other processors or the peripheral devices they want to communicate they are sending some requests to the microprocessor that they want the control of its buses now in response to that request the microprocessor generates the grant signals that it has granted the request it has accepted the request and it has granted that to the other processors or the peripheral devices they can have a control over its system buses ok so whenever the peripheral devices they are communicating they send these request signals and in respect to these request signals microprocessor issues the grant signals so when the the processors they are going to request the CPU to release the control of the system bus and when this request is received by the CPU it sends the acknowledgment means it is going to send the grant signal okay now suppose that two input/output devices they want to communicate at the same time so two requests will be generated so how to decide the priority the priety is decided that our qng do not it has the highest priority or higher priority than our two and gt1 so first this first the system buses will be given to the processor which is connected at this GG knot and then at gt1 okay so in the pin diagram we have seen that we have studied all the pins we have first we studied the power signals like VSS and the VCC then we studied the address and the data bus then the address and stator signals then we studied the ready here s reset test Q s naught Q s 1 and the status signals also there then n mi int R non-maskable interrupt interrupt request clock signals then we have the the pin number 31 and to pin number 24 these pins they have dual functions means they can work as in the minimum mode also their function is different and in maximum mode their function is different now if we want to relate it with the signal diagram of a zero eight six then we can see that this is the signal diagram and if we relate it with the pin diagram we have the power signals VCC ground here connected okay then we have the clock input here then we have interrupt interface signals mean signals which are related with the interrupt operation of 8 0 8 6 so for interrupt we have the int R then int a signal non-maskable interrupt and the test signal then reset signal it is used to clear the contents of or to restart the execution of eight zero eight six okay then we have hold and h lda which are used went for the DMA interface whenever the eight zero eight six it is interfacing with the DMA controller direct memory access controller then these two signals are used then we have the mode select signal is the minimum and the maximum mode selection then we have memory input/output controls like we have memory input output signal which decide that whether the operation it’s a memory operation or an input/output operation then we have read/write data enabled ready signal data transfer transmit and receive signal this is bus high enable or the status signal 7 then address latch enable so whenever any memory or input/output operations are performed then these signals are used then we have the multiplex address and the data purse ad not to AD 15 and then we have the a 16 to a 19 but address bus which is also used as the status signals s 3 to s 6 so all the pins on this pin diagram they are categorized into various signals in this signal diagram so the description of the pins and the signal it remains the same only just you have to categorize the pins in various signals ok so in this video we studied about the pin diagram and the signal diagram of the 8:08 6 micro processor so I hope that this topic is clear to you thank you

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