Interfacing Memory with 8086 Microprocessor – Problem 1 – Microprocessor for Degree Engineering

Interfacing Memory with 8086 Microprocessor – Problem 1 – Microprocessor for Degree Engineering


Do subscribe to Ekeeda channel and press bell icon to get updates about latest Engineering HSC and IIT-JEE Mains and Advanced videos.Hello Friends, In this video we will solve a problem based on how we can interface of memory chip with 8 0 8 6 Microprocessor so let us take a problem. So our problem is we have to interface to 4K into 8 EpROMS and tWO 4K into 8 ram chips with 8 0 8 6 Microprocessor and we have to select suitable address map now you’re in the question we are having – wrong and – RAM chips okay the to roam chips they are each of the size four K into eight and the two ram chips they are also of the size four K into eight so if we talk about the room we are having total 8 kilobyte and for the RAM we are also having 8 kilobyte so to address these memory chips how many address lines of the 8 0 8 6 microprocessor are required we can calculate by using the formula 2 raised to the power N equals to capital n where n it is the number of memory locations in the memory chip and n is the number of address lines now number of memory locations we can calculate we know that 1 kilobyte of memory it has 1 0 to 4 memory locations if we are having 4 kilobyte of memory we are having 4 0 9 6 memory locations so if we are having 8 K memory then we can calculate the number of memory locations for 0 9 6 + 4 0 9 6 so that will be the total number of memory locations so if we calculate the number of address lines we can calculate by using this formula so 2 raised to the power N equals 2 this 4 0 9 6 + 4 0 9 6 ok so if we calculate the number of address lines it will come out to be 13 because 2 raised to the power 13 equals to 8 kilobyte of memory so number of address lines n equals to 13 here so 13 address lines will be required to address these 4 memory chips – for the role and – for the rap ok now it’s 0 8 6 this microprocessor it is having 20 address lines from a knot to a 19 now out of these 20 address lines only 13 are required to address the memory chip that is from a knot to a 12 the remaining address lines from a 13 to a 19 they will be used to form the chip select signal along with the bus high enable signal bhe and the a not address line okay now when we have studied about those steps or the procedure when we interface the memory with the 8:08 6 microprocessor so in that procedure our first step is to is to arrange the available memory chips in such a way that we get a complete 16-bit date of it okay we want 16-bit data with here now each memory chip you can say that it can store it it bit of data at each memory location but we want 16-bit date of it so we are going to arrange the two rams and two rooms in parallel to each other so that when two rams are arranged then upper ample will give us the odd address and the lower ram it will give us the even address so when we talk about the arrangement of these four memory chips we will arrange it like this so that each is providing a tidbit of data so together they will give us the 16 bit of data one will give us act as odd memory bank second will act as the even address memory bank this is for roll and this is for RAM so for RAM you will have one for the odd and but for the even address memory bank so in this way we are going to arrange the memory chips now next step will be to find out the address map because in the question we were asked that we have to select the suitable address map for addressing these memory chips so we will use the 13 address lines from a node to a 12 of the 8 0 8 6 microprocessor to address these roam and RAM memory chips let’s see that what the address will come out to be you so there are 28 rest lines of the microprocessor now out of these 20 address lines may have to use only 13 address lines so from a knot to eight well they will be used by us okay now we are having two memory chips for the RAM and two memory chips for the row so we can use a address line 813 to differentiate between the RAM and the row okay now remaining address lines are 813 to 819 so we are going to use these address lines for the chip selects signal and these address lines are for addressing the chips okay now if we will decide for the room so for room if we take that a 13 it is taking the value 1 and 1 these are not to 8 well they can take any values they can all be 0 or they can all be at 1 okay so there can be any of the combinations here okay from 0 0 to 1 bar 1 and this a 13 it is always at logic 1 because here we are using this address map for the room now these 8 13 to 8 19 we are using for selecting the chip selects signal so this a 13 to a 90 it will be at logic 1 and this is all we are taking for the Rome and Rome the sizes 8 K into it because we are having two memory chips each has got 4k and four kilobyte of memory so total we are having rome 8 kilobyte so the address range it will come out to be if we combine this this will be 1 1 1 1 means f 1 1 1 0 that means if we are having the 0 then it will be e then again 0 again 0 and then 0 so the address will come out to be f e 0 0 0 H and if we take this value then it will be F F F F F H it means that this address is in the hexadecimal notation and this is the address f e 0 0 0 1 1 1 1 this will be F 1 1 1 0 it will be e then 0 0 0 0 it will be 0 then again 0 0 0 0 it will be the next 0 and again 0 0 0 0 so it will be the next 0 so if this is in the hexadecimal notation we are getting the address range as this for the EP row memory chips now coming to the RAM RAM is also of the same size 8 K into 8 so again the addresses now we are using this a 13 for the selection that whether room is there or Ram is connected so we can change this value we can have 0 for the RAM and these a 0 to a 12 these 13 address lines they can take n value okay so it can be zero zero zero till 1 bar 1 1 so these 13 address lines they can take any value from 0 0 to 1 part 1 this 0 0 we are taking this a 13 to select the room and the RAM so this is for RAM also these lines a 19 to a 14 they will be at logic one so if we calculate the address the address will come out to be F C 0 0 0 H and this will be F D F F F H 1 point 1 1 4 F 1 1 0 1 4 D then again 1 1 1 4 F again this will form the F F and F here 1 1 1 1 4 F then 1 1 0 0 4 C then again 0 0 0 V I have it this address so you can see here that the this is for RAM and this is also of the size 8 K into 8 because we are having 2 RAM chips ok now here if we see the addresses here at C 0 0 till mdff and after that we are having F 0 0 till F F F F so you can see that this lab and Rome their addresses they are continuous there is no gap between their address map so because in the question we were asked that we have to sue use though we have to select a suitable address map if it is given in the question that use the absolute decoding here so that the address map it is continuous if it is asked in the question that choose the address match such that it is continuous then you can use this type of addressing where we will use the 813 address line it can take one value also it can take zero value also so zero it will take four RAM and one it will take four Rome okay so addresses we have got okay now we are going to draw the interfacing so it that how we will interface these four memory chips with the microprocessor because we have to use the remaining address lines plus the bus high enable signal and a knot to form the chip selects signal so here we will use our decoder for it the decoder will be a three is to 8 decoder the three lines are the input lines and eight will be the output lines so three inputs will be the address line bhe and the a node and eight outputs they will be used to select the four memory chips okay so let’s draw the interfacing circuit for it you these are the four memory chips you this is our 3 is 2 8 decoder the input lines to this decoder will be the 3 input lines so 3 input lines will be a naught a 1 and a 2 a naught will be the bus high enable bhe a 1 will be our a not address line and also we are using the 813 address line so a the third input line will be the 813 address lines the remaining address lines we are using to select this decoder this decoder is having three enable lines even e 2 and E 3 e 1 and E 2 are active low and III is active high now this is an gate 7 4309 gate is there we are having the remaining address line a 14 a 15 to a 19-8 13 is already as one input line a 14 is there and a 14 to a 19 we have connected to the NAND gate to enable this decoder now rule this room will have a chip select signal here which will be called cs1 this will be C as 2 this will be C is 3 and C is for now these chips are like signals they are active low signals so we have denoted here bubble also the room because the for room if we want to read the data from here so we will have an output enable signal so for these four memory chips we have the 4 chip select signals and these chips are like signals they are active flow so here we have denoted bubbles over all these ship selects signals now the this is the threes to a decoder we are having 3 inputs so we will have the 8 output lines here now these are put lines they are they are denoted like oh not oh one zero two zero three zero four oh five six and Oh seven we are having bubbles over here so it will be an active flow means when we are having zero zero zero so this first Oh nan will be zero if we are having zero zero one then old one will be zero that will be activated so no signal will be available over this now if we form a table for the combinations of these three inputs and what will be the output let’s draw the table these are the three inputs of the decoder and a2 is representing the 813 a dress line a1 is representing the a knot and a notice representing the bus high enable signal so these are the address or the bus high labor and these are the inputs to the decoder now these three inputs they can take different different values like 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 & 1 1 1 so 3 inputs can have 8 computations now we will require only 6 from these 8 computations because 2 will be used for the chips alike signal 1 2 will be for this – for this and 2 for this so we are having we will use only six combinations remaining two combinations we can lift so if it is 0 0 0 then the operation perform will be even an odd address in RAM so here both even and odd addresses of the RAM will be selected so we can say that a word is transferred on V naught 2 D 15 means total 16-bit data because even a dress is also 8-bit order dresses also 8-bit here if we see this is 4 or this is also for odd this is for even and this is also for even so we are having on addresses from the Roman DRAM and even addresses from Rome and am also so if we are using the first combination zero zero zero then even and odd addresses and the ramp will be selected if we are using 0 0 1 then only even address in the ramp if we are having 0 1 0 then only odd address is there in them so even address means eight 8-bit address is being transferred so it means one byte by transfer on d7 to D naught and then ordered dress is there then byte transfer is on D 8 to be 15 we will use the upper order data bus and the lower order data bus will be used for the even address so these three combinations are used for the yeah now we are left with 1 2 3 4 5 combinations so out of these five combinations we will use only 3 combinations that is 1 0 0 1 0 1 and 1 1 0 so when it is 1 0 0 then both even an N or address in Rome will be selected when it is 1 0 1 then only even address and if it is 1 1 0 then only the or address and they are in the room so we are using these three combinations for the role selection ok if it both even in order there then we will have the word transfer mean 16-bit data is going to be transferred if it is only even and odd address then bite transfer will take place so this is the table where we have the three inputs of the decoder and how the eight outputs they will be used for selecting the chips for the chip select one we will have because this is for the odd so for odd address in the room or a dressing room we have 1 1 0 so order dress in the room we will use the fourth and the sixth combination because we want this 1 0 0 also and 1 1 0 also so this fourth and the sixth output of the decoder they will be used to form the chip select signal for the room similarly for the chip select number 2 because we want the even address in the room so for even address we will have this 1 0 0 also and this 1 0 1 also so we will use the output number fourth and fifth for forming the chip selects signal for this room for dam we have the this is for all so for or Ram we will have 0 1 0 and 0 0 0 so we are going to use the 0 and the second output of the decoder for even we are going to use the 0 and the first output so if we form the chip select signals we will use to engage here this is for chip select one chip select two chip select three and chip select four chip select three and four for the RAM and one in two are for the row one is for the Ordre c is to the strip select two it is for the even room this is cs3 it is for or DRAM and this is for even RAM so per chip select one we will have fourth and sixth four chips are like two we will have fourth and fifth for chip select three we will have two and 0 and for chip select 4 we will have 1 and Z so this is how the output of the decoder they are combined they are used to form the chip select signals we have used the three inputs because in the steps we studied that we have to use the bus I enable signal also we have to use the a not address line also and the 13 address line is also used so these outputs they will be connected accordingly to this logic to the chip selects signals of all the four memory chips now also here we have to connect the read and the write signals data lines are also there so for odd we will use the higher order address line and for even they are going to use the lower order address line here also d82 d15 for the odd and D not to d7 further even then the room is also is only for the read operation so the memory read signal of the microprocessor will be connected here at the output enable line of the roam chips here we are having a forum we have both read and write so read and write signals of the microprocessor they will be connected here address lines are also there because we are using the 13 address lines to address these memory chips and remaining address lines we have used for you are forming the chips alike signals so your we will have the 13 address lines connected so this is how we can interface the four memory chips which are of the size 4k into eight with the microprocessor we can via your use the three is to 8 decoder to form the chip select signal so in this video we have solved a problem based on how we can interface the memory chips with the 8 0 8 6 microprocessor first we will calculate that how many address lines are required to address these memory chips and then the remaining address lines which are left we will use our logic circuit to obtain the chip select signals for the memory chips and then we will connect the corresponding control signals for the read and write operation of the microprocessor to the read and write signals of the memory chips ok so in this way you can solve the problems which are based on interfacing the memory with 8 0 8 6 microprocessor I hope that this problem is clear to you thank you

22 thoughts to “Interfacing Memory with 8086 Microprocessor – Problem 1 – Microprocessor for Degree Engineering”

  1. 1 ram has 4K memory locations => it should have A0-A11 lines(i.e 12 address lines) . but according to you A0-A12(13 address lines).isn't it wrong? 29:10

  2. you have taken two chips of each RAM and ROM. But you have taken the total memory of 8k only, which is for either 2 RAMs or 2 ROMs or each RAM and ROM. why is the total memory 8k=4k+4k and not 16k=8k+8k.
    ma'am its urgent, please consider replying.

  3. How can you use A0 in both address decoding logic and address line in each chip? you have to use A1 to A13 as address line for each chip

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